1. Field of the Invention
The invention relates generally to the field of low dielectric constant dielectric layers. More particularly, the invention relates to the utilization of low dielectric constant dielectric layers within composite dielectric layers employed within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by microelectronics dielectric layers.
As microelectronics integration levels have increased and patterned microelectronics conductor layer linewidth dimensions have decreased, it has become more common within the art of microelectronics fabrication to employ low dielectric constant dielectric layers formed interposed between the patterns of patterned microelectronics conductor layers within microelectronics fabrications. Low dielectric constant dielectric layers are desirable interposed between the patterns of patterned microelectronics conductor layers within microelectronics fabrications since such low dielectric constant dielectric layers typically provide microelectronics fabrications with enhanced microelectronics fabrication speed, reduced microelectronics fabrication parasitic capacitance and attenuated patterned microelectronics conductor layer cross-talk.
Of the methods and materials which may be employed for forming low dielectric constant dielectric layers interposed between the patterns of patterned microelectronics conductor layers within microelectronics fabrications, methods which employ low dielectric constant dielectric materials such as but not limited to organic polymer spin-on-polymer (SOP) dielectric materials (including but not limited to polyimide organic polymer spin-on-polymer (SOP) dielectric materials, poly (arylene ether) organic polymer spin-on-polymer (SOP) dielectric materials and fluorinated poly (arylene ether) organic polymer spin-on-polymer (SOP) dielectric materials), amorphous carbon dielectric materials (including fluorinated amorphous carbon dielectric materials) and silsesquioxane spin-on-glass (SOG) dielectric materials (including but not limited to hydrogen silsesquioxane (HSQ), carbon bonded hydrocarbon silsesquioxane and carbon bonded fluorocarbon silsesquioxane (FSQ) dielectric materials) are particularly desirable within the art of microelectronics fabrication. Such methods and materials are desirable due in particular to the ease of fabrication of dielectric layers by spin-on methods or by chemical vapor deposition (CVD) methods, and the resulting low dielectric constant of the dielectric layers, which typically exhibit homogeneous dielectric constant values ranging from about 2.5 to about 3.3. For comparison purposes, conventional silicon containing dielectric layers formed of silicon containing dielectric materials such as but not limited to silicon oxide dielectric materials and silicon nitride dielectric materials employed within microelectronics fabrications typically exhibit homogeneous dielectric constants within a range of from about 4.0 to about 4.4.
While low dielectric constant dielectric layers have found increasing applications within microelectronics fabrications, their employment in microelectronics fabrications is not without problems. In particular, there is often observed delamination of a silicon containing dielectric cap layer from a low dielectric constant dielectric layer. In addition, there is frequently a need for a barrier layer impervious to moisture to protect a low dielectric constant dielectric layer from degradation.
Various methods have been disclosed within the art of microelectronics fabrications for forming composite dielectric layers with desirable properties within microelectronics fabrications The provision of adequate adhesion between the component layers of a composite dielectric layer structure is a primary object of the art, as is the capability of filling gaps and other non-planar features of the underlying surfaces of substrates employed in microelectronics fabrications. These objects are achieved by methods which are conventional in the art such as spin-on methods, chemical vapor deposition (CVD) methods and plasma assisted chemical vapor deposition (PECVD} methods. In particular, the enhancement of adhesion of silicon oxide layers to spin-on-polymer (SOP) dielectric layers has been the object of improvement in the art of microelectronics fabrication.
For example, Sayka, in U.S. Pat. No. 5,472,825, discloses a method for forming with attenuated interfacial void a composite dielectric layer comprising a plasma enhanced chemical vapor deposited (PECVD) silicon oxide layer upon which is formed a spin-on-glass (SOG) dielectric layer. The method employs plasma etchback of siliconoxide layer formed employing plasma enhanced chemical vapor deposition (PECVD) method prior to forming the spin-on-glass (SOG) dielectric layer thereon.
Further, Jang, in U.S. Pat. No. 5,536,681, discloses a method for forming a composite dielectric layer comprising a silicon oxide layer formed employing plasma enhanced chemical vapor deposition (PECVD) method as a topographic underlayer upon which is formed a silicon oxide dielectric overlayer formed employing an ozone assisted thermal chemical vapor deposition (CVD) method employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material. The method employs a selective nitrogen plasma treatment of upperlying portions of the silicon oxide dielectric topographic underlayer such that the silicon oxide overlayer is formed with attenuated voids in the silicon oxide overlayer.
Still further, Yeh, in U.S. Pat. No. 5,614,279, discloses a method for forming a single liquid phase deposited (LPD) layer of silicon oxide with improved physical and electrical properties. The method employs an oxygen or hydrogen plasma treatment of the single liquid phase deposited (LPD) silicon oxide layer once formed.
Finally, Jang et al., in U.S. Pat. No. 5,726,090, disclose a method for forming a composite dielectric layer from: (1) a silicon oxide layer formed employing an ozone assisted thermal chemical vapor deposition (CVD) method employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material upon: (2) a silicon oxide trench fill layer formed employing thermal oxidation, with attenuated voids within the silicon oxide layer formed by the thermal chemical vapor deposition (CVD) method. The method employs forming a nitrogen plasma treated silicon oxide layer formed by plasma enhanced chemical vapor deposition (PECVD) interposed between the ozone assisted chemical vapor deposited (CVD) silicon oxide overlayer and the silicon oxide underlayer formed by thermal oxidation.
It is therefore towards the goal of forming within microelectronics fabrications low dielectric constant dielectric layers with enhanced adhesion to overlying silicon containing dielectric layers that the present invention is more generally directed.
Desirable in the art of microelectronics fabrication are additional methods and materials which may be employed for forming a composite dielectric layer comprising a low dielectric constant dielectric layer with enhanced adhesion formed employing an organic polymer spin-on-polymer (SOP) dielectric material within a microelectronics fabrication.